BLOCK FLOATING POINT-BASED FPGA IMPLEMENTATION APPARATUS AND METHOD FOR FBLMS ALGORITHM

摘要

A block floating point-based FPGA implementation apparatus and method for an FBLMS algorithm. Said method comprises: an input buffer and conversion module performing block buffering and recombination on a reference signal, converting same into a block floating-point system, and then performing FFT; a filtering module performing filtering in a frequency domain and performing dynamic truncation; an error calculation and output buffer module performing block buffering on a target signal, converting same into a block floating-point system, subtracting the target signal from a filtering output signal, and converting same to a fixed-point system, so as to obtain a final cancellation resu and a weight adjustment and calculation module and a weight updating and storing module acquiring an adjustment amount of a weight, and updating the weight according to blocks. A block floating-point data format and a dynamic truncation method are used for to a recursive structure of an FBLMS algorithm, ensuring that data has a relatively large dynamic range and relatively high precision, solving the conflict between performance, speed, and resources, and also improving the reusability and expandability by means of a modular design.