A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

Muhammad H. Rais; Syed M. Qasim

首页> 外文期刊>International journal of computer science and network security >A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

【24h】

A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

机译：使用基于S-Box的质数减少残差的AES-128的新颖FPGA实现

获取原文

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of advanced encryption standard (AES-128) algorithm based on the design of high performance S-Box built using reduced residue of prime numbers. The objective is to prese

机译：在本文中，我们基于使用减少质数残数构建的高性能S-Box的设计，提出了一种高级加密标准（AES-128）算法的新颖的现场可编程门阵列（FPGA）实现。目的是提出

著录项

来源
《International journal of computer science and network security》 |2009年第9期|共5页
作者
Muhammad H. Rais; Syed M. Qasim;
展开▼
作者单位

展开▼
收录信息
原文格式 PDF
正文语种
中图分类自动化技术、计算机技术;
关键词

相似文献

外文文献
中文文献
专利

1. A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box [J] . Muhammad H. Rais, Syed M. Qasim International journal of computer science and network security . 2009,第9期

机译：使用基于S-Box的质数减少残留的AES-128的新颖FPGA实现
2. Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs | Science Publications [J] . Mohammed H. Al Mijalli American journal of applied sciences . 2011,第8期

机译：使用Virtex-5和Virtex-6 FPGA有效实现基于S-Box的质数减少残差|科学出版物
3. Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs [J] . Mohammed H. Al Mijalli American journal of applied sciences . 2011,第8期

机译：使用Virtex-5和Virtex-6 FPGA有效实现了基于S-Box的质数减少后的残差
4. Resource Efficient Implementation of S-Box Based on Reduced Residue of Prime Numbers using Virtex-5 FPGA [C] . Muhammad H. Rais, Syed M. Qasim World Congress on Engineering . 2010

机译：基于使用Virtex-5 FPGA的素数减少的S盒资源高效实现
5. An Automated Design Space Exploration Tool for OpenCL-Based Implementations on FPGAs Using Machine Learning [D] . ?Naher, Jannatun 2020

机译：自动化设计空间探索工具针对OpenCL 为基础实现在FPGA上使用机器学习
6. Real-Time Digital Signal Processing Based on FPGAs for Electronic Skin Implementation [O] . Ali Ibrahim, Paolo Gastaldo, Hussein Chible, 2017

机译：基于FPGA的电子皮肤实现实时数字信号处理
7. Efficient Realization of S-Box based reduced Residue of Prime Numbers using Virtex-5 and Virtex-6 FPGAs [O] . Mohammed H. Al Mijalli 2011

机译：使用Virtex-5和Virtex-6 FPGA有效实现了基于S-Box的质数减少后的残差

A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

摘要

著录项

相似文献

相关主题

期刊订阅