FPGA-Based Hardware Implementation of Image Processing Algorithms for Real-Time Vehicle Detection Applications.

摘要

It is well known that vehicle tracking processes are very computationally intensive. Traditionally, vehicle tracking algorithms have been implemented using software approaches. The software approaches have a large computational delay, which causes low frame rate vehicle tracking. However, real-time vehicle tracking is highly desirable to improve not only tracking accuracy but also response time, in some ITS (Intelligent Transportation System) applications such as security monitoring and hazard warning. For this purpose, this thesis makes an attempt to design a hardware based system for real-time vehicle detection, which is typically required in the complete tracking system. The vehicle detection systems capture pictures using a camera in real-time and then we apply several image processing algorithms, such as Fixed Block Size Motion Estimation (FBSME), Reconfigurable Block Size Motion Estimation (RBSME), Variable Block Size Motion Estimation (VBSME) and Mixtures of Gaussian, to process these images in real-time for vehicle detection.;We first propose the Very-Large-Scale Integration (VLSI) implementation for RBSME algorithm, which supports arbitrary block size motion estimation. Experiment results show that the proposed architecture achieves the flexibility of adjustable block size at the expense of only 5% hardware overhead compared to the traditional design.;We then propose a low-power VLSI implementation for the VBSME algorithm, which employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solutions. The fast full-search algorithm is based on the comparison of the current minimum Sum of Absolute Difference (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We first experimentally decide on the specific conservative lower bound and then implement the fast full-search algorithm in Field-Programmable Gate Array (FPGA). To the best of our knowledge, this is the first time that a fast full-search block matching algorithm is explored to reduce power consumption in the context of VBSME, and designed in hardware. Experiment results show that the proposed hardware implementation can save power consumption by 45% compared to conventional VBSME designs based on the non-fast full-search algorithms.;At last, we propose an System-on-a-Chip (SoC) architecture for an Mixture of Gaussian (MoG) based image segmentation algorithm. The MoG algorithm for video segmentation application is computational intensive. To meet real-time requirement of high frame rate high resolution video segmentation tasks, we present a hardware implementation of the MoG algorithm. Moreover, we integrated the hardware IP into an SoC architecture, so that some key parameters, such as learning rate and threshold, can be configured on-line, which makes the system extremely flexible to adapt to different environments. The proposed system has been implemented and tested on Xilinx XtremeDSP Video Starter Kit Spartan-3ADSP 3400A Edition. Experiment results show that under a clock frequency of 25MHz, this design meets the real-time requirement for Video Graphics Array (VGA) resolution (640 × 480) at 30 frame-per-second (fps).