Design Optimization in Write Speed of Multi-Level Cell Application for Phase Change Memory

机译：相变内存的多级单元应用程序写入速度的设计优化

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摘要

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

机译：通过使用物理尚未分析的Compact PCM模型，可以实现改进相变存储器的写入速度的设计优化。我们的仿真结果表明，可以优化连续脉冲编程方案的写入速度，并且优于多级单元应用的慢淬火方案。

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《IEEE International Conference of Electron Devices and Solid-State Circuits》|2009年||共4页
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作者
Jun-Tin Lin; Yi-Bo Liao; Meng-Hsueh Chiang; I-Hsuan Chiu; Chia-Long Lin; Wei-Chou Hsu; Pei-Chia Chiang; Shyh-Shyuan Sheu; Yen-Ya Hsu; Wen-Hsing Liu; Keng-Li Su; Ming-Jer Kao; Ming-Jinn Tsai;
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中图分类 TN4-53;
关键词
Phase change memory; PCM; MLC;

机译：相变存储器;PCM;MLC;

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专利

1. Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM) [J] . Namba Kazuteru, Lombardi Fabrizio IEEE Transactions on Computers . 2019,第2期

机译：多级单元（MLC）相变存储器（PCM）中减少写延迟的编码
2. ×10 Fast write, 80% energy saving temperature controlling set method for multi-level cell phase change memories to solve the scaling blockade [J] . Koh Johguchi, Toshimichi Shintani, Takahiro Morikawa, Solid-State Electronics . 2013,第mara期

机译：×10快速写入，节能80％的节能温度控制设置方法，用于多级单元相变存储器，解决缩放阻塞
3. Modified write-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe [J] . Gang Zhang, Zhe Wu, Jeung-hyun Jeong, Solid-State Electronics . 2012,第期

机译：改进的写入验证方案，用于使用掺Ge的SbTe改善多级单元相变存储器的耐久性
4. Design Optimization in Write Speed of Multi-Level Cell Application for Phase Change Memory [C] . Jun-Tin Lin, Yi-Bo Liao, Meng-Hsueh Chiang, IEEE International Conference of Electron Devices and Solid-State Circuits . 2009

机译：相变内存的多级单元应用程序写入速度的设计优化
5. Architectural techniques for multi-level cell phase change memory based main memory. [D] . Jiang, Lei. 2014

机译：基于多级单元相变存储器的主存储器的架构技术。
6. Scandium doping brings speed improvement in Sb2Te alloy for phase change random access memory application [O] . Xin Chen, Yonghui Zheng, Min Zhu, -1

机译：dium掺杂为相变随机存取存储器应用带来了Sb2Te合金速度的改善
7. FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory [O] . Lei Jiang, Youtao Zhang, Bruce R. Childers, 2012

机译：FpB：细粒度功率预算，提高多级单元相变存储器的写入吞吐量

Design Optimization in Write Speed of Multi-Level Cell Application for Phase Change Memory

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