Low stress multi-level reading method and a multi-level phase change memory device of the phase-change memory cell

摘要

An object of the present invention is to provide a multi-level reading method and a multi-level phase change memory device of the phase-change memory cell. A bit line 9 and the PCM cell 2 is selected first, the first bias voltage (V _BL, V ₀₀₎ to the selected bit line is applied. The first read current flowing to its selected bit line in response to the first bias voltage (I _RD00) is compared with a first reference current (I _00). The first reference current, lower than the first read current is a first reference current if the selected PCM cell is in the reset state, otherwise, is that higher it. The selected PCM cells, based on a comparison of the first read current and the first reference current I to determine whether a reset condition. If it is not in the reset state, the first bias voltage greater than the second bias voltage (V _BL, V ₀₁₎ is applied to the bit line 9 is selected. .BACKGROUND