In this paper, the gate-voltage dependent source/drain (S/D) resistance (R_(SD)) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of (R_(SD)) is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.
展开▼
机译：在本文中，通过实验和模拟检查掺杂剂隔离（DS）肖特基屏障（SB）结中的栅电压依赖源/漏极（S / D）电阻（R_（SD））。将重点放在完全耗尽的UTB-SOI MOSFET上，具有在低温下实现的ASI S / D的PTSI S / D。在用DS建模SB-S / D时，确定观察到的性能增强是否由Si中的高度掺杂浅层或通过导致SB高度降低的界面偶极度引起的诱导性能增强是具有挑战性的。模拟显示（R_（SD））的栅极电压依赖性对于偶极效应更强。对于在该工作中检查的DS-S / D的SB-MOSFET，当SBH降低与高浓度浅掺杂结合时，模拟使测量数据具有出色的拟合。
展开▼
