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Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

机译:具有负肖特基势垒高度的电触点感应的具有源极和漏极的纳米线晶体管

摘要

A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
机译:纳米线晶体管包括与沟道区电耦合的未掺杂的源极区和漏极区。与栅极导体电隔离的源极堆叠包括界面层和源极导体,并且沿源极区域的至少一部分完全同轴地包裹在源极区域周围。源极导体和源极区域之间的肖特基势垒是负肖特基势垒,并且在半导体源极区域中感应出自由电荷载流子的浓度。

著录项

  • 公开/公告号US10833199B2

    专利类型

  • 公开/公告日2020-11-10

    原文格式PDF

  • 申请/专利权人 ACORN SEMI LLC;

    申请/专利号US201916693143

  • 申请日2019-11-22

  • 分类号H01L29;H01L29/786;B82Y10;H01L29/417;H01L29/775;H01L29/78;H01L29/08;H01L29/06;H01L29/423;

  • 国家 US

  • 入库时间 2022-08-21 11:27:24

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