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IMPLEMENTING TSV FOR 3D SEMICONDUCTOR PACKAGING

机译:实现3D半导体包装的TSV

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The current market driver for semiconductor package technology is to provide more functionality and improve performance without increasing package size. Vertically configured 3D package technology addresses this issue for a broad number of enterprise products. Initially, the 3D package contained two or more semiconductor die elements mounted on top of one another, most often interconnected using a common substrate interposer. Adapting through silicon via (TSV) technology for die-on-die interface on the other hand has the potential to further improve both package performance and package assembly efficiency. Progress in this area has accelerated through the cooperation and joint development programs between a number of government, industry and technical universities. Although the TSV process is touted as the 'next big thing' in semiconductor packaging, capabilities and methodologies for providing wafers and die elements for stacking currently vary a great deal between suppliers. Although TSV technology has the potential to revolutionize semiconductor packaging, it currently remains hostage to a very limited homogeneous family of products; MEMS, memory and image sensors. In addition, there are a number of processes and methodologies that are considered proprietary and may require licensing agreements and additional fees for there use. Industry roadmaps, however, continue to point toward the eventual use of TSV in developing new generations of high performance system-in-package products. This paper will explore three basic approaches to TSV formation, viafirst, via middle and via-last: Via-first integration forms very small via holes in the wafer prior to front-end processing. The via-middle formation follows front-end wafer level processes. Via-last integration will occur after bonding wafers or joining individual die elements to one another (Die-on-Die). Due to the increased thickness of pre-joined die, the via-last process typically provides somewhat larger via holes.
机译:用于半导体封装技术的当前市场驱动程序是提供更多功能并提高性能而不增加封装尺寸。垂直配置的3D包技术为广泛的企业产品解决了此问题。最初,3D封装包含两个或更多个半导体管芯元件,其彼此顶部安装在一起,通常通常使用公共基板插入器互连。另一方面,通过用于模具导通界面的硅通孔(TSV)技术具有进一步提高封装性能和封装组装效率的可能性。该地区的进展通过了许多政府,工业和技术大学之间的合作和联合发展方案加速。虽然TSV过程被吹捧为半导体封装中的“下一个大事”,但是用于提供晶圆和堆叠的模具元件的能力和方法目前在供应商之间变化很大。尽管TSV技术有可能彻底改变半导体包装,但目前仍然是一个非常有限的均匀产品的人质; MEMS,内存和图像传感器。此外,还有许多流程和方法被认为是专有的,可能需要许可协议和使用的额外费用。然而,行业路线板继续指出最终使用TSV在开发新的高性能系统内容产品中的产品。本文将探讨TSV地层,ViaFirst,中间和通孔的三种基本方法:通过第一集成在前端处理之前晶片中的非常小的通孔形成。通孔中间形成遵循前端晶片级工艺。将在粘接晶片或将单个模具元件彼此连接(模具芯片)之后发生通孔的积分。由于预连接管芯的厚度增加,通孔最后的过程通常通过孔提供稍微较大的孔。

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