Back-End Copper Plating for 3D and Wafer Level Packaging Applications-(PPT)

机译：用于3D和晶圆级包装应用的后端铜电镀 - （PPT）

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Applications of Cu Plating for 3D Packaging Technical Comparison of Various Cu Processes Bump (stud and pillar) RDL (redistribution line) and Embedded Passives TSV (through-silicon-via)

机译：CU电镀对三维封装技术比较的应用凸块（螺柱和支柱）RDL（再分配线）和嵌入式无线TSV（通过硅通）

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《SMTA 3D/SiP Advanced Packaging Symposium》|2007年||共22页
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Bioh Kim; Charles Sharbono; Marvin Bernt;
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中图分类 TN401-53;
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2. Implementation of silicon-on-glass MEMS devices with embedded through-wafer silicon vias using the glass reflow process for wafer-level packaging and 3D chip integration [J] . Chiung-Wen Lin, Chia-Pao Hsu, Hsueh-An Yang, Journal of Micromechanics and Microengineering . 2008,第2期

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3. Experimental Studies of Through-Wafer Copper Interconnect in Wafer Level MEMS Packaging [J] . Sung-Hoon Choa Key Engineering Materials . 2006,第Pt1期

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4. Back-End Copper Plating for 3D and Wafer Level Packaging Applications-(PPT) [C] . Bioh Kim, Charles Sharbono, Marvin Bernt SMTA 3D/SiP Advanced Packaging Symposium . 2007

机译：用于3D和晶圆级包装应用的后端铜电镀 - （PPT）
5. Experimental and Simulation Board Level Reliability Assessment of Wafer Level Chip Scale Packages (WCSPs) Under Thermal Cycling [D] . Khan, Hassaan Ahmad 2015

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7. Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint [O] . Wang, Xiaojing, Bleiker, Simon J., Antelius, Mikael, 2017

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Back-End Copper Plating for 3D and Wafer Level Packaging Applications-(PPT)

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