Current Status and Perspective of High-k Gate Stack Materials Engineering for Further Scaled CMOS

摘要

High-k dielectric materials and technology have been intensively investigated over the past ten years, and are now just at the stage before production. A number of new challenges and hopes have been found. Some of these challenges are related to processing or material optimization issues. This is because the optimal process parameters must be different from those currently used in poly-Si/SiO{sub}2/Si system. However, most issues seem to be related to the intrinsic properties of high-k dielectric materials. We would, therefore, like to discuss some key challenges that must be addressed to further advance Si-CMOS.