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Breakdowns in high-k gate stacks of nano-scale CMOS devices

机译:纳米级CMOS器件的高k栅堆叠中的击穿

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摘要

New failure mechanisms associated with breakdown in high-k gate stack consisting of HfO_2/SiO_x bilayered structure are presented. In addition to dielectric-breakdown-induced epitaxy (DBIE) commonly found in breakdowns in poly-Si/SiO_xN_y and poly-Si/Si_3N_4 MOSFETs, grain-boundary and field-assisted breakdowns near the poly-Si edge are found. A model based on breakdown induced thermo-chemical reactions has been developed to describe the physical microstructural damages triggered by breakdown in the high-k gate stack and the associated post-breakdown electrical performance. Some abnormal post-breakdown electrical behaviors such as recouping of the transistor's saturated drain current, percolation resistance and transconductance are found to be common for high-k MOSFETs. Grain-boundary enhanced breakdown in annealed HfO_2 films is of critical importance in degrading the reliability of high-k gate stacks.
机译:提出了与HfO_2 / SiO_x双层结构组成的高k栅堆叠中击穿相关的新失效机理。除了通常在多晶硅/ SiO_xN_y和多晶硅/ Si_3N_4 MOSFET的击穿中发现的介电击穿引起的外延(DBIE)外,在多晶硅边缘附近还发现了晶界和电场辅助击穿。已经开发了基于击穿引起的热化学反应的模型,以描述由高k栅极堆叠击穿和相关的击穿后电性能触发的物理微观结构破坏。发现一些异常的击穿后电气行为,例如晶体管饱和漏极电流的恢复,渗流电阻和跨导对于高k MOSFET来说很常见。退火的HfO_2薄膜中晶界增强的击穿对于降低高k栅堆叠的可靠性至关重要。

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