A Defect Model for Metallic Carbon Nanotubes in Cell-based Logic Circuits

摘要

This paper presents a model and a corresponding detection technique for nano scaled defects arising from the presence of metallic carbon nanotubes. Using an optimal layout of cells based on Carbon Nanotube Field Effect Transistors (CNTFET) in a circuit netlist, such defects are modeled by traditional single stuck-at faults (SSF) and detected by SSF test sets. Simulation results are presented to evaluate the performance of the proposed technique in modeling and detection of metallic CNT defects. It is shown on average 96.77% of metallic CNT defects can be detected for the seven largest ISCAS89 benchmark circuits.