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From oxide breakdown to device failure: an overview of post-breakdown phenomena in ultrathin gate oxides

机译:从氧化物分解到装置故障:超薄栅极氧化物中崩溃现象的概述

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The time to breakdown (t{sub}(BD)) of SiO{sub}2/SiON gate oxides strongly decreases when oxide thickness (T{sub}(OX)) is scaled from 3 nm to 1 nm. However, the oxide BD does not necessarily cause an immediate circuit failure because the device performance is not always severely degraded after the BD [1-3]. This is important for circuit reliability because an extra lifetime margin can be obtained from the post-BD phase. Pursuing these ideas, at least three different approaches have been proposed to deal with the post-BD reliability: the progressive BD (PBD) approach [4,5], the hard breakdown (HBD) prevalence ratio method [6] and the successive BD approach [7,8]. The PBD approach is based on the observation that a certain time is required in ultra-thin oxides for the progressive growth of the BD current up to a value that perturbs the device performance. The HDB prevalence ratio approach is based on the existence of two BD modes, HBD and soft BD (SBD). Since, in this approach, it is assumed that only HBD causes the device failure, the failure distribution relevant to reliability is that of HBD instead of that of the first BD event, thus obtaining a lifetime increase which depends on the so called HBD prevalence ratio (α{sub}(HBD)). Finally, the successive BD approach is based on the assumption that all the BD events which occur under operation conditions in ultra-thin oxides are SBDs. The chip failure is considered to occur when a fixed number of such events have occurred in any device of the chip [7] or in the chip as a whole [8], thus obtaining a significant lifetime improvement. In this paper, we present an overview of post-BD phenomena in ultrathin (1 nm < T{sub}(OX) < 3 nm) oxides and couple this description to a discussion of the different methodologies proposed to deal with the post-BD reliability. We focus on the complete description of the statistics of the time to device failure (t{sub}(FAIL)) and of the residual time (t{sub}(RES)) from oxide BD to device failure, and on their scaling properties. Both intrinsic and extrinsic BD modes will be considered and the impact of burn-in will be briefly analyzed.
机译:当氧化物厚度(T {sub}(ox))从3nm到1nm缩放时,SiO {sub} 2 / sion栅极氧化物的击穿(t {sub}(bd))强烈降低。然而,氧化物BD不一定会导致立即电路故障,因为在BD [1-3]之后,器件性能并不总是严重降级。这对于电路可靠性非常重要,因为可以从BD阶段获得额外的寿命余量。追求这些想法,至少提出了三种不同的方法来处理BD后可靠性:进展BD(PBD)方法[4,5],硬击穿(HBD)流行率比例[6]和连续的BD方法[7,8]。 PBD方法基于观察结果,在超薄氧化物中需要一定时间,用于BD电流的逐步生长至扰动器件性能的值。 HDB流行率比方法是基于两个BD模式,HBD和软BD(SBD)的存在。由于在这种方法中,假设只有HBD导致设备故障,与可靠性相关的故障分布是HBD而不是第一个BD事件的故障分布,从而获得终身增加,这取决于所谓的HBD流行率(α{sub}(hbd))。最后,连续的BD方法基于假设在超薄氧化物中的操作条件下发生的所有BD事件是SBD。当在芯片[7]的任何设备中或作为整体的芯片中发生固定数量的这样的事件时,考虑芯片故障发生,从而获得显着的寿命改进。在本文中,我们概述了超薄(1nm

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