Analysis and Verification of DDR3/DDR4 Board Channel Impact on Clock Duty-Cycle-Distortion (DCD)

摘要

In this paper, the clock DCD jitter will be investigated and the results will be compared for two channel configurations: using a general UDIMM topology and using discrete SDRAM component topology. The outcome studies will show the primary factors contributed on clock DCD in a most common DDR channel configurations. The simulated differential clock DCD data will be provided while changing channel impedance corners for package and PCB in a reflective discrete DRAM component and a lossy UDIMM configurations. The simulated differential DDR clock DCD analysis will be verified with the measured clock DCD jitter amount in actual system configurations.