机译:用于UDIMM和离散SDRAM组件配置的DDR3 / DDR4时钟占空比失真(DCD)的分析和比较
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Intel Corporation, Programmable Solutions Group (PSG) 101 Innovation Drive, San Jose, CA, USA;
Distortion; Topology; Reflection; SDRAM; Jitter; Field programmable gate arrays; Signal restoration;
机译:用于DDR3和DDR4 SDRAM的快速锁定无谐波数字DLL
机译:具有双时钟系统,四相输入启动和低抖动全模拟DLL的1.5V 3.2 Gb / s / pin图形DDR4 SDRAM
机译:DDR3 SDRAM中电源断开的故障特征分析
机译:DDR3 / DDR4板通道对时钟占空比 - 失真(DCD)的分析与验证
机译:集成的多学科设计优化,使用离散灵敏度分析对几何复杂的气动弹性构型进行优化。
机译:在基于变异成分的COGA数据链接分析中比较离散环境和连续环境
机译:DDR3 sDRam标准技术分析