DDR3与FPGA接口的高速电路板信号完整性分析

摘要

由于芯片频率的提高,现今高速PCB设计的信号完整性问题的分析已经成为不可忽略的关键环节.以FPGA控制DDR3 SDRAM读写数据的高速PCB板为硬件平台,论述高速PCB设计中的反射、串扰等信号完整问题并以Cadence公司的SPECCTRAQuest仿真器作为仿真工具,提出并验证了抑制反射和串扰的方法.仿真结果表明,端接电阻可抑制反射,且不同端接方式以及驱动端频率不同,抑制反射的效果有所不同;改变布线间距及走线长度可抑制串扰.通过布线前和布线后的仿真来指导PCB的设计,保证了硬件平台的正常工作.%As the chip frequency increases,the signal integrity analysis in today′s high-speed PCB design has become the key link that cannot be ignored. Taking the high-speed PCB as the hardware platform,in which FPGA controls the reading and writing data of DDR3 SDRAM,the signal integrity problems of reflection and crosstalk in high-speed PCB design are elaborated. With the SPECCTRAQuest simulator made by Cadence Company as the simulation tool,the method of suppressing the reflection and crosstalk is put forward and verified. The simulation results show that the terminating resistor can suppress reflection,and the suppression effect varies with different termination modes and different frequencies of the drive end;changing the wire rout-ing interval and wiring length can suppress crosstalk. The simulation experiments before and after wire routing were performed to guide the PCB design,so as to ensure the normal running of the hardware platform.