Design and Verification of Embedded Passive Circuits in LTCC Substrates for High-Performance, Low Cost RF SiP Modules

摘要

We present a design process for complex embedded RF circuits in LTCC substrates, used in a System-in-Package (SiP) module. Our process utilizes a unique and highly efficient simulation method for the embedded passive circuits, and can also estimate the manufacturing cost of the substrate in commercially available high-volume LTCC processes. These features are essential for developing a SiP module where the substrate and RFIC are co-optimized for high performance at minimum size and cost. LTCC is an attractive medium for embedding complex RF/wireless passive circuits because of its multiple wiring layers and excellent electrical properties. However, the substrate design process for a SiP module has proven to be quite challenging because of the need to account for interactions and parasitic capacitances of all components, while trading off component values between the substrate and the IC. Traditional design methods for embedded components often utilize separate models for individual embedded components, or alternatively use a three-dimensional field solver. Neither of these methods is satisfactory because they pose design limitations and lack insight into the equivalent circuit-model representation, which is the best vehicle for designing to account for interactions and parasitics. Our substrate design process uses a custom Partial-Element Equivalent-Circuit (PEEC) simulator that provides accuracy comparable to that of full-wave solvers in the RF/wireless frequency range, but at simulation speeds that are 100 to 1000 times faster. This simulator also emphasizes equivalent circuit model representation of the entire substrate. Experimental verification of several illustrative test circuits confirms the simulation accuracy. These results validate the PEEC modeling approach for building complex embedded RF circuits in LTCC.