An integral approach to reuse verification code towards post silicon test pattern generation, design validation and analysis for effective SoC product development

摘要

This paper proposed an integral approach for post silicon pattern generation that allows testing of verification code in simulation directly on wafer level of SoC design or packaged SoC devices for efficient delivery of bug-free tester patterns. This is done by running and debugging the test pattern directly on the silicon wafer or packaged devices with specific hardware setups on a wafer probing machine or a specially designed lab-based evaluation board. The traditional method of pattern delivery involves debugging of patterns on tester which incurs more cost on tester time and resources. These overheads can be greatly reduced with the integrated approach that eases the reliance on testers to debug the patterns. An additional advantage of the approach is the enhanced capabilities in the validation and failure analysis of SoC functionalities, which reduces wastage and resulted in a faster product development cycle.