Reuse and automatic generation of testbenches for effective hardware verification.

摘要

It is well known that functional verification has become the major bottleneck of the entire design process due to the high complexity of modern circuit designs. There is an emerging need for a practical solution to reduce the functional verification time. New verification methodology and tools are being developed and are well used in the process of project design. As design reuse has been very popular in complex device development, a methodology of verification reuse is a key point to reduce time in verification stage. An automated generation tool can contribute to reduce verification time by relieving engineers from code generation and debugging.;This thesis provides a general review of functional verification, which analyzes existing methodologies. We focus on testbench reuse. We present a method, Function Abstraction (FA), to generate reusable testbenches at functional level. Then, a method is presented to capture system functionality with the system description language (SDL). System functional abstraction is common to all modules designed from the same specification. That makes it possible to build testbenches at this functional level aimed to reuse testbenches. Adapting the techniques FA and SDL language, we introduce a methodology to build functional reusable testbench components. In addition, a rule-based technique is used to develop a tool to implement this methodology. Rules define which information is needed to build testbenches and how to process this information.;The result of this research is a testbench generation tool that follows our reusable testbench generation methodology, to build reusable testbench components with the e language, a Hardware Verification Language (HVL).