Flip Chip Technology has begun to gain acceptance in electronics assembly due to its improved electrical performance and smaller size than most standard packages. The conventional flip chip process is not easily compatible with Surface Mount Technology (SMT) and therefore a lot of work has been done to improve the materials and processes involved. Based on this work, No Flow underfills were developed to make the flip chip process more transparent to SMT. Assembly and Cost modeling showed that no flow underfills could reduce cost by close to sixty percent when compared to conventional underfill processes ar d reduce the assembly time by close to fifty percent. The cost savings are most noticeable when the number of die per panel increases. Due to the unique qualities of No Flow underfills, a number of new processing challenges have arisen. These include the substrate design, dispense pattern, die placement, and reflow issues. Substrate design can have a great effect on the flow of the materials during dispense and placement processing steps. The dispense pattern can also affect the amount of voiding seen in the finished assemblies especially as the die size increases. As no flow materials have some viscosity, they can require a higher placement force than conventional flip chip processing. As no flow materials are designed to simultaneously reflow and cure in the same profile, the reflow process is extremely important to the yield of the components. Reliability results from various studies have shown that No Flow underfills can survive more than 1000 cycles in both Air-to-Air Thermal Cycling (AATC) and Liquid-to-Liquid Thermal Shock (LLTS). The reliability of the materials can be affected by the size of the die, the bump pattern, and the pad definition method. Failure mode analysis of the assemblies have shown that No Flow materials tend to exhibit fillet cracking and bulk underfill cracking in higher frequencies than delamination, but solder fatigue is still the main ultimate end failure.
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