Low-k materials etch and strip optimization for sub 0.25 /spl mu/m technology

摘要

With the introduction of low-k materials into the intermetal dielectric (IMD) layers, it is important to optimize the via etch process in order to minimize the IMD degradation that is caused by harsh O/sub 2/ and wet stripping treatments. A simple, sensitive, and cost-effective measurement method is introduced for the determination of low-k material degradation caused during the via etch process. By using a single damascene comb structure, a large sidewall area of low-k material can be exposed to the etch strip process in question. The intra-line capacitance between the trenches is an extremely sensitive parameter to evaluate material degradation. Using this method, etch and strip processes can be tailored for a specific low-k material, which in turn, improve the interconnect performance and via yield. The results from this method are identical to results coming from the optimization of electrical performance with completely integrated chips and is in very good agreement with FTIR analysis for bare films.