High density through-wafer electrical interconnects for direct-chip-attach, device-scale MEMS packaging

摘要

This paper otulines the motivation behind, and fabrication process for, a novel through-wafer electrical interconnect structure. The interconect was designed in order to test the feasibility of routing electrical signals through full thickness silicon wafers. The completed interconnect is compatible with solder-based direct-chip-attach (DCA) processing and CMOS circuitry. The core of the t hroughj-wafer electrical interconnect structure consists of a high-aspect-ratio via which is subsequently insulated and metallized. On the wafer backside, an under bump metallurgy (UBM) is added around the via opening and a solder bump is formed to complete the