The next generation of communication devices like smart-phones and tablets require smaller integrated circuits with a large number of signal I/O's to support higher performances. Flip chip interconnect technology has traditionally been driven by electrical performance and package miniaturization. As the IC's become smaller and higher performing with advancements in silicon nodes (45nm, 28nm and beyond), the need for fine pitch flip chip technology is of paramount importance. Copper pillar fine pitch flip chip (CuP-FPFC) packaging technology enables devices with a bump pitch less than 60um to meet electrical, thermal and dimensional requirements of the application. Previous studies have shown that thermo-compression bonding in presence of a nonconductive paste (TCNCP) is a robust process for manufacturing CuP-FPFC packages. To achieve reliable solder joints with highest assembly yields it is of paramount importance to optimize heating profile of the TCNCP process. In this paper, a transient conduction model is presented to predict and optimize rapid heat flow patterns through various stages of the TCNCP process.
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