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Advanced/3D Packaging and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks

机译:先进/ 3D包装和材料完整性:压力诱导的芯片互连堆叠新超低k电介质的效果和力学性能

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The reliability-limiting effects in 3D IC structures using TSVs including mechanical stress distributions and the resulting effects on material integrity (e.g. failure modes like interface .delamination, cohesive cracking, metallurgical degradation at joints, and chip-package interaction)and finally on device performance degradation are challenges in advanced 3D integration technologies and product development [1]. Managing internal mechanical stress is a key task to ensure high reliability of products manufactured in advanced CMOS technology nodes, and it is a highly ranked concern for 3D TSV technologies [2]. It requires the determination of materials properties, including Young's modulus, Poisson ratio and coefficient of thermal expansion (CTE), for each material used. Particularly for sub-m structures, materials properties change depending on the size of the structure. For some materials, especially the materials used in packaging, these characteristics are a non-linear function of temperature, i. e. temperature-dependent materials data have to be determined [3]. For. polycrystalline materials, their microstructure has to be considered. In this talk, the determination of mechanical properties like Young's modulus, and fracture toughness will be discussed for the elements of Cu/Low-k interconnect stacks, but also cohesive and adhesive failure in thin film stacks. Double cantilever beam (DCB) testing provides the energy release rate of thin films. Nanoindentation experiments are usually used to measure the elastic modulus of thin films, however, this technique is able to provide fracture toughness information as well. A wedge-shape indenter is used to delaminate ULK films locally. The fracture energy associated with the indentation induced delamination is evaluated considering the pore densification process. The fragile nature of ultra low-k dielectrics, particularly nanoporous organosilicate glasses (OSGs), and the packaging-induced mechanical stress are reliability concerns for advanced/3D packaged products. We demonstrate that novel synthesis approaches to manufacture nanoporous materials with optimized topology, particularly self-assembly processes, are able to control pore size and pore topology. Particularly, elastic modulus values close to the Hashin-Shtrikman upper bound can be reached for thin films with periodically arranged pore structures with constant pore size [4].
机译:3D IC结构中的可靠性限制效应使用TSV,包括机械应力分布和对材料完整性的产生影响(例如,界面的故障模式,接头,接头的粘性开裂,冶金劣化,以及芯片包相互作用),最后对装置性能劣化是先进3D集成技术和产品开发中的挑战[1]。管理内部机械应力是确保高级CMOS技术节点制造的产品的高可靠性的关键任务,并且对3D TSV技术进行了高度排名的担忧[2]。对于每种材料,需要确定使用杨氏模量,包括杨氏模量,泊松比和热膨胀系数(CTE)。特别是对于子M结构,材料特性根据结构的尺寸而变化。对于一些材料,特别是包装中使用的材料,这些特性是温度的非线性函数,I。 e。必须确定温度依赖的材料数据[3]。为了。多晶材料,必须考虑它们的微观结构。在该谈判中,将讨论Cu / Low-K互连堆叠的元件等杨氏模量等机械性能,也可以讨论薄膜叠层的内聚和粘合衰竭。双悬臂梁(DCB)测试提供薄膜的能量释放速率。通常用于测量薄膜的弹性模量的纳米indentation实验,然而,该技术也能提供裂缝韧性信息。楔形压模用于本地分解ULK薄膜。考虑孔隙致密化过程,评估与压痕诱导分层相关的断裂能。超低k电介质,特别是纳米多孔有机硅酸盐玻璃(OSG)和包装诱导的机械应力的脆弱性是对先进/ 3D包装产品的可靠性问题。我们表明,用优化拓扑制造纳米多孔材料,特别是自组装工艺的新型合成方法能够控制孔径和孔隙态。特别地,对于具有恒定孔径的周期性布置的孔结构,可以达到靠近Hashin-Shtrikman上粘合的弹性模量值[4]。

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