Transport Properties of 3D Vertically Stacked SiGe and SiGeC Nanowires

摘要

One of the trends in microelectronics is to explore nanowire gate-all-around structures and alternative channel materials with superior properties. We investigate the electrical transport in three-dimensional (3D) vertically stacked germanium-enriched nanowires. Two starting materials have been used for the nanowire fabrication: SiGe and SiGeC. Measurements using the Pseudo-MOSFET concept show that the transport in as-grown gateless nanowires is controlled by the voltage applied on the substrate, as in a MOS transistor. Interestingly, the substrate bias effect depends on the designed geometry of the nanowire. For high width/length ratio nanowires, we show the possibility of turning on both electrons and holes channels. For nanowires with small width/length ratio, only the hole channel is visible. Transport modification with the concentration of germanium in the nanostructures is also discussed.