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Resist fundamentals for resolution, LER and sensitivity (RLS)performance tradeoffs and their relation to micro-bridging defects

机译:抵制决议,LER和敏感性(RLS)性能权衡的基本基础及其与微桥接缺陷的关系

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High NA immersion and EUV lithography processes are challenged to meet stringent control requirements for the 22 nmnode and beyond. Lithography processes must balance resolution, LWR and sensitivity (RLS) performance tradeoffswhile scaling resist thickness to 100 nm and below". Hardware modules including coat, bake and development seek toenable resist processes to balance RLS limitations. The focus of this paper is to study the fundamentals of the RLSperformance tradeoffs through a combination of calibrated resist simulations and experiments. This work seeks to extend the RLS learning through the creation of calibrated resist models that capture the exposurekinetics, acid diffusion properties, deprotection kinetics and dissolution response as a function of PAG loading in a 193nm polymer system. The calibrated resist models are used to quantify the resolution and sensitivity performancetradeoffs as well as the degradation of resist contrast relative to image contrast at small dimensions. Calibrated resist simulations are capable of quantifying resolution and sensitivity tradeoffs, but lack the ability to modelLWR. LWR is challenging to simulate (lattice models) and to measure; due to the dependence on spectral frequency.This paper seeks to use micro-bridging experiments as means to better understand the statistical nature of LWR. Micro-bridging analysis produces a statistical distribution of "discrete bridging events" that encompasses practical variationsacross scanner, track and resist. Micro-bridging and LWR experiments are done using a 1.2 NA immersion system on 45nm space structures (90 nm pitch) as a means to demonstrate the concept, but the methodology can also be used to studyEUVL processes as the technology matures. The understanding of the RLS performance tradeoffs enables TEL todevelop future hardware and processes that support industry scaling goals.
机译:高NA浸泡和EUV光刻工艺的挑战是要满足22 nmnode超越严格的控制要求。光刻工艺必须平衡分辨率,LWR和灵敏度(RLS)性能tradeoffswhile缩放抗蚀剂厚度为100纳米和下面的”硬件模块包括涂层,烘烤和发展寻求平衡RLS局限性toenable抗蚀剂的方法。本文的重点是研究通过校准的组合RLSperformance权衡的基本面抗蚀仿真和实验。这项工作的目的通过建立校准的抗蚀剂模型捕获exposurekinetics,酸扩散性质,脱保护动力学和作为PAG负载的函数的溶解反应的延长RLS学习在193nm的聚合物系统,该校准的抗蚀剂模型是用于量化分辨率和灵敏度performancetradeoffs以及在小尺寸的抗蚀剂相对于图像对比度的对比度。校准抗蚀剂模拟是能够量化分辨率和灵敏度权衡的降解,但缺乏能力modelLWR:L WR是具有挑战性的模拟(晶格模型)和测量;由于对频谱frequency.This纸的依赖旨在利用微桥接实验作为手段来更好地理解LWR的统计性质。微桥接分析产生包围实用variationsacross扫描器,跟踪和抗蚀剂“离散的桥接事件”的统计分布。微桥接和LWR实验是使用45纳米空间结构(90纳米节距)为说明概念的装置的1.2 NA浸没系统完成,但方法也可用于处理studyEUVL随着技术的成熟。在RLS性能折衷的理解,使TEL todevelop未来的硬件和工艺支持行业比例的目标。

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