N-Channel Complementary Pairing in Nitride Trap Memory

摘要

Providing sufficient VT window is a key challenge to scaling non-volatile memories. Nitride trap memories, like the Twin MONOS device [1] shown in Fig. 1, have a simple process, and higher coupling ratios and lower program and erase voltages than conventional floating gate. However nitride trap memory suffers from VT window closure after cycling and retention due to mismatch recombination and surface state traps. Endurance capability can be improved by implementing block-level reference circuits that use actual memory cells to match cycling conditions to improve endurance capability [2].