SYSTOLIC ARCHITECTURE FOR TRANSPOSITION-FREE VLSI IMPLEMENTATION OF SEPARABLE 2-D DWT

摘要

In this paper, we present a novel systolic implementation of separable two-dimensional (2-D) discrete wavelet transform (DWT). Unlike the existing structures, the proposed design does not require any input/output network or additional hardware unit for transposition of intermediate output matrix. Consequently, it provides a significant saving of hardware and computation-time. It has 100% hardware utilization efficiency, and offers higher throughput rate with significantly less area-time complexity compared with the existing structures.