The effects of surface treatment by a dilute HF rinse on the drain current - gate voltage characteristics in HgFETs have been investigated by experimental measurements and numerical simulations. The apparent threshold voltage increases and interface trap density decreases with time after the HF rinse is due to a coupling between the Si film/BOX interface and the positively charged, hydrogen-terminated surface acting as a back gate in the thin-film folly depleted HgFET.
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