ULTRA-LOW THERMAL BUDGET CMOS PROCESS FOR 65NM-NODE LOW-OPERATION-POWER APPLICATIONS

摘要

Flash lamp annealing (FLA) enhances the drivability of pFETs with the solid phase epitaxial extension junction. The increase in the junction leakage of the extension junction is less than 1 order of magnitude as compared with that fabricated with conventional spike RTA on a 300mmt wafer. Adding moderate RTA after FLA combined with fluorine implantation has been found to recover the interfacial damage created by FLA. Excellent Vth control at 35run gate length without halo implantation and a high switching speed at 0.9V power supply are demonstrated for 65nm-node LOP (Low Operation Power) applications.