A New Two-Step Recess Technology Using SiN{sub}x Passivation and Pt-Buried Gate Process and Its Application to 0.15μm Al{sub}0.6InAs/In{sub}0.65GaAs HEMTs

摘要

Recently, InP-based HEMTs have shown excellent high speed characteristics by reducing the gate length (L{sub}g) to sub-50nm range [1] and developing two-step recess (TSR) process [2]. Especially, thin InP etch-stopper acted as good surface passivation, which was effective to suppress Kink effect by minimizing the surface reaction mechanisms between impact-ionization induced holes in the narrow band-gap (E{sub}g) InGaAs channel and surface states on side-recessed region [2, 3]. However, this technology might give rise to the low Schottky barrier height (SBH) and the possible plasma induced damage in the epitaxial structure during Ar-based RIE, and lead to the problem of reliability related with side-recessed void region. In this paper, a new voidless TSR technology will be developed using SiN{sub}x passivation and Pt-buried gate process.