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Ge deep sub-micron pFETs with etched TaN metal gate on a High-K dielectric, fabricated in a 200mm silicon prototyping line

机译:GE深亚微米PFET在高k电介质上蚀刻棕褐色金属栅极,在200mm硅原型制品中制造

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We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.15 μm. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO_2 dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N_(it)) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent High-K gate dielectric deposition to push EOT values below Inm is illustrated.
机译:我们首次报告在深亚微米GE PFET上,物理栅极长度低至0.15μm。这些装置是使用硅样工艺流程制造的,具有由ALD或MOCVD HFO_2电介质上的棕褐色栅极组成的直接蚀刻栅极堆叠。找到有希望的驱动电流。解决了各种问题,如严重的短信效应(SCE),与SI和大量接口状态相比的二极管泄漏增加(N_(IT))。示出了对替代GE基板预处理和随后的高k栅极电介质沉积以推动低于INM的EOT值。

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