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Post-OPC verification using a full-chip pattern-based simulation verification method

机译:使用全芯片模式的仿真验证方法后OPC验证

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In this paper, we evaluated and investigated techniques for performing fast full-chip post-OPC verification using a commercial product platform. A number of databases from several technology nodes, i.e. 0.13um, 0.11um and 90nm are used in the investigation. Although it has proven that for most cases, our OPC technology is robust in general, due to the variety of tape-outs with complicated design styles and technologies, it is difficult to develop a "complete or bullet-proof" OPC algorithm that would cover every possible layout patterns. In the evaluation, among dozens of databases, some OPC databases were found errors by Model-based post-OPC checking, which could cost significantly in manufacturing - reticle, wafer process, and more importantly the production delay. From such a full-chip OPC database verification, we have learned that optimizing OPC models and recipes on a limited set of test chip designs may not provide sufficient coverage across the range of designs to be produced in the process. And, fatal errors (such as pinch or bridge) or poor CD distribution and process-sensitive patterns may still occur. As a result, more than one reticle tape-out cycle is not uncommon to prove models and recipes that approach the center of process for a range of designs. So, we will describe a full-chip pattern-based simulation verification flow serves both OPC model and recipe development as well as post OPC verification after production release of the OPC. Lastly, we will discuss the differentiation of the new pattern-based and conventional edge-based verification tools and summarize the advantages of our new tool and methodology: 1). Accuracy: Superior inspection algorithms, down to 1nm accuracy with the new "pattern based" approach 2). High speed performance: Pattern-centric algorithms to give best full-chip inspection efficiency 3). Powerful analysis capability: Flexible error distribution, grouping, interactive viewing and hierarchical pattern extraction to narrow down to unique patterns/cells.
机译:在本文中,我们使用商业产品平台评估和研究了用于执行快速全芯片验证的技术。来自多个技术节点的许多数据库,即在调查中使用0.13um,0.11um和90nm。虽然它已经证明,对于大多数情况而言,我们的OPC技术通常是强大的,因为由于设计风格和技术复杂的磁带出版物,难以开发一个“完整或防弹”OPC算法每种可能的布局模式。在评估中,在数十个数据库中,通过基于模型的opc检查来发现一些OPC数据库,这可能在制造 - 掩模版,晶片过程中显着成本,更重要的是生产延迟。从这种全芯片OPC数据库验证中,我们了解到,优化OPC模型和在一组有限的测试芯片设计上的配方可能无法在该过程中生产的设计范围内提供足够的覆盖范围。并且,仍可能发生致命错误(例如捏合或桥梁)或差的CD分布和处理敏感模式。结果,多个掩模版带传出循环并不罕见,以证明在一系列设计中接近过程的模型和配方。因此,我们将描述一个全芯片模式的仿真验证,在OPC的生产释放后,验证OPC模型和配方开发以及Post OPC验证。最后,我们将讨论新的基于模式和基于边缘的验证工具的差异,并总结了我们的新工具和方法的优势:1)。精度:卓越的检查算法,下降到1nm精度,采用新的“基于模式”方法2)。高速性能:以模式为中心的算法,以提供最佳的全芯片检测效率3)。强大的分析能力:灵活的错误分发,分组,交互式视图和分层模式提取,以缩小到唯一的图案/细胞。

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