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High- Density Packaging Technologies on Silicon Substrates

机译:硅基板上的高密度包装技术

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We have developed high-density packaging technologies with Cu/photosensitive benzocyclobutene (BCB) multi-layer on a silicon substrate. We have adopted stacked via structure as multi-layer and a silicone as a core substrate. The core substrate is composed of silicon using metal through plugs. The interconnects consist of stacked via with 20μm via and 30μm land, and the via is filled by electroplating. The conductor layer was formed by semi-additive process using copper sputtering layer as seed metal. The width of the patterned line is 5μm and the space between them is also 5μm. The through-hole was 10μm in diameter and 170μm deep, which was formed deep-RJE etching. The holes have been filled with electroplating Cu and Cu/Ag conductive paste, which makes it possible to form the via on via and via on through plug. Since such stack structure makes connection length short between LSI and a board, the reduction of delaying time for signal propagation could be improved. We have evaluated electrical performances of the Cu/BCB substrate with fine conductive line. The width of the line is from 6μm to 11 μm, and the length is from 5.0mm to 15.0mm to study the dependence of signal attenuation behavior on the line length and width. S-parameter of micro strip line structure was measured by network analyzer. The transmission power loss of 6|im width, 15mm length line was less than -3dB in the range of up to 16GHz frequency.
机译:我们在硅衬底上开发了具有Cu /光敏苯并丁烯(BCB)多层的高密度包装技术。我们已经采用了通过结构堆叠为多层和硅氧烷作为芯基板。核心基板由硅通过塞塞组成。互连由堆叠的通孔组成,通过20μm和30μm的焊盘,并且通过电镀填充通孔。通过使用铜溅射层作为种子金属的半添加过程形成导体层。图案化线的宽度为5μm,它们之间的空间也为5μm。通孔的直径为10μm,深度为170μm,形成深rje蚀刻。孔已经填充有电镀Cu和Cu / Ag导电浆料,这使得可以通过塞子形成通孔和通孔。由于这种堆叠结构使LSI和板之间的连接长度短,因此可以提高信号传播的延迟时间的降低。我们已经评估了用细导线的Cu / BCB基板的电性能。线的宽度为6μm至11μm,长度为5.0mm至15.0mm,以研究信号衰减行为对线长度和宽度的依赖性。通过网络分析仪测量微带线结构的S参数。 6 |传输功率损耗为6 | IM宽度,15mm长度线的频率低于-3dB,频率高达16GHz。

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