Advances in Fine Pitch Lead Free Assembly Process

摘要

This research focuses on evolving the best possible criteria for selecting high electrical performance 100 micron pitch lead free solder bumping process. This is achieved through modeling and simulating the pad, process, reliability and test strategy. Coplanar waveguides (CPW) were modeled to evolve process criteria for pad design and choice of materials. Polyimide was chosen as the passivation on the chip. Further signal parasitics were studied for the passivation and a selection criterion was evolved for its thickness. The pad and the passivation layers were studied for dielectric loss when subjected to thermal cycling (air to air). This evaluation leads to the selection of the best pad configuration for lead free solder. An in-depth study on how internal resistance of the solder contributes to the change in parasitics is presented through numerical and simulated models. Standard under bump metallurgy (UBM) was used on the pads. Lead free solder (Sn3.5AgO.3Cu) was chosen as the bumping material. Bumping strategy was evolved by which solder can be deposited on the UBM without stencil printing or electroplating. Flip chip B-stage underfill was also evaluated for wafer level application and standardized. This paper concludes by suggesting the best design, process and reliability criteria which should be adopted for lead free solder 100 μm pitch flip-chip.