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Numerical Simulation of Underfill Cure Evolution in Chip-Scale-Package (CSP) Manufacturing Process

机译:芯片尺度包装(CSP)制造过程中底部填充固化进化的数值模拟

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In direct-chip-attachment (DCA) a chip is mounted directly to a substrate using a grid-array of solder bumps. In order to minimize the thermal stress, it is necessary to use underfill encapsulants to improve the reliability of flip-chip solder joint interconnections. By applying an underfill encapsulant into the gap between the IC chip and the substrate, the stress on the solder joints during each temperature excursion can be uniformly dispersed throughout the encapsulated module, leading to an enhanced improvement of the reliability. In addition, underfilling a flip chip assembly can also provide an environmental protection against corrosion of the ICs. In an actual manufacturing process establishing efficient during of the underfill is of paramount importance, as it is directly linked to the fatigue reliability of the part. Unfortunately, there are a number of parameters, such as, curing kinetics of underfill resin, temperature profile in reflow oven, solder bump temperature, and solder hump patterns that interact with each other in determining the degree of cure. This paper gives an overview of a numerical software package developed to address this critical issue of predicting the degree of cure of underfill during an actual manufacturing process, along with some case studies. This software package is intended to serve as a design tool, which would facilitate the process engineer to adjust the parameters mentioned above to obtain the desired degree of cure for a reliable package.
机译:在直接芯片附接(DCA)中,使用焊料凸块的网格阵列直接安装到基板上。为了使热应力最小化,必须使用底部填充密封剂来提高倒装芯片焊接接头互连的可靠性。通过将底部填充封装剂施加到IC芯片和基板之间的间隙中,在每个温度偏移期间的焊点上的应力可以均匀地分散在整个封装的模块中,从而提高可靠性的提高。另外,底部填充芯片组件还可以提供针对IC的腐蚀的环境保护。在建立欠填充期间的实际制造过程中,底部填充的高效是至关重要的,因为它与部分的疲劳可靠性直接相关。不幸的是,存在许多参数,例如,固化底部填充树脂的动力学,回流烘箱中的温度曲线,焊料凸块温度和焊料驼峰图案在确定固化程度时相互作用。本文概述了开发的数字软件包,以解决预测实际制造过程中底部填充程度的关键问题,以及一些案例研究。该软件包旨在用作设计工具,这将促进过程工程师调整上述参数,以获得可靠包的所需的固化程度。

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