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μPGA SOCKET AND SOLDER JOINT RELIABILITY STUDY

机译:μPGA插座和焊点可靠性研究

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Reliability of a Micro Pin Grid Array Socket interposer and interconnect solder joint for μPGA processor are studied. The socket is feature with Zero-Insertion-Force (ZIF) mechanism for the contact connection to the processor. The unique sliding cover and contact fingers design allow the interconnection of μPGA from conventional large force insertion operation to quasi-zero force of solid contact by the compliance of pin and stiffness of finger. The major rationale of design and application are to enhance manufacturability in both insertion assembly and rework. To assess the reliability of the socket and solder joint and identify the process window in the early stage of product development cycle, a test vehicle (TV) with daisy chain (DC) construction, separation header and test via access are designed for failure detection and isolation during the realtime monitoring in Accelerated Temperature Cycling test. This paper will describe the methodology of consolidating the package and board level reliability assessment to facilitate the potential of shortening the product development cycle. Design of Experiment (DOE) is extensively used from process development to package reliability assessment. Various inspection methods are used in the pre-processing IQA stage to assess the package and PCB physical properties. With reflow-emulated thermal process applied on the socket and PCB, the Shadow Moire was also used to monitor the package wrapage on global and μPGA locations. Interconnect Stress Test (IST) will be performed to ensure the via wall strength integrity and trace quality during pre-conditioning and thermal cycle. Fatigue fracture mode and life cycle will be, analysis by 5DX, Dye Penetrant, failure analysis, and Weibull distribution of the failure of the solder joint. Contact resistance will be measured with 4-wire setting and its reliability response in the thermal cycling will be compared to the lognormal accumulative failure of the solder joint in future study. Conjunction with FEM analysis endeavor on stress/strain response of the solder joint under bending load, a mechanical stress emulation approach is proposed to fundamentally look insight of its correlation to the reliability scale and eventually resolve current quasi-brittle solder cracking issue in the electronic industry.
机译:研究了微引脚阵列插座插槽和μPGA处理器互连焊接接头的可靠性。套接字是具有零插入力(ZIF)机制的功能,用于与处理器的接触连接。独特的滑动盖和接触手指设计允许通过销和手指刚度的依从性的函数与固体接触的准零力的互连允许μPGA互连。设计和应用的主要基本原理是提高插入组件和返工中的可制造性。为了评估插座和焊接接头的可靠性,并在产品开发周期的早期阶段识别过程窗口,使用菊花链(DC)施工,通过访问的分离头和测试设计,用于故障检测和加速温度循环试验中实时监测期间的隔离。本文将描述巩固包装和董事会级别可靠性评估的方法,以促进缩短产品开发周期的可能性。实验(DOE)的设计广泛地从过程开发中使用,以包装可靠性评估。在预处理IQA阶段使用各种检查方法来评估包装和PCB物理性质。利用在插座和PCB上施加的回流仿真热过程,影子莫尔也用于监测全局和μPGA位置的包装包装。将进行互连应力测试(IST),以确保在预处理和热循环期间通过壁壁强度完整性和痕量质量。疲劳骨折模式和生命周期将分析5DX,染料渗透,失效分析,焊接失效的威布分布。接触电阻将用4线设置测量,并且在未来的研究中将与热循环中的可靠性响应进行比较。 FEM分析的结合致力于弯曲载荷下焊接接头的应力/应变响应的响应,提出了一种机械应力仿真方法,从根本上看起来与可靠性规模相关的相关性,最终解决电子工业中的当前准脆性焊料开裂问题。

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