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NEW 3D STACKED TECHNOLOGY SYSTEM FOR PoP/SiP ELECTRIC COMPONENTS

机译:用于POP / SIP和电气元件的新型3D堆叠技术系统

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The need for advanced high-performance systems in the rapidly booming digital consumer electronic market, (i.e.: cellular phones, digital cameras, etc) is ever spiraling upward. SiP (System in a Chip) technology is a powerful means to achieving miniaturizing and manufacturing of such high-performance electronics equipment. Some of the advantages of SiP when used in such electronics equipment offers overall flexibility due to its small size, thin type, and high-speed transmission rates, combined with low-power consumption and low-cost allowing for the best all-around technology. There are several SiP methods available; SoP (System on Package) is most notable to offer faster-time-to-market and it's ease of re-design as its greatest advantages. In particular, the PoP/SiP JISSO method called "Spiral Contact" (Micro Contact technology) is a unique market created by Advanced Systems Japan (ASJ) which offers solutions in a 3D stacked system array. Features of 3D stacked technology system are: (1) Only KGD (Known Good Die) will be accumulated, which in turn drops the bad yield problem to minimal numbers, and the restrictions when applied in the semiconductor and electronic parts sector are minimal. (2) It is also very flexible in allowing manufacturers the ability and ease to work with specification changes especially in memory capacity etc. because it allows individual chips to be layered (or stacked in 3D). (3) The consolidation of the passive components (resistors, capacitors, coil, etc.) is also possible. (4) By combining several chips into one package shortens the inter-chip wiring distance. (5) As a result, the influence of EMI (Electro-Magnetic Interference) noise is reduced, increasing stability while simultaneously increasing high-speed operation. (6) In addition, the bus design of the wiring for the high-speed operation between the microcomputer and memory, etc. becomes unnecessary, simplifying both design and reducing manufacturing costs in the process. (7) As a result, time to market is drastically reduced. (8) And this makes it easier to create a total system solution proposal without worrying about expensive development costs.
机译:需要在快速蓬勃发展的数字消费电子市场先进的高性能系统,(即:手机,数码相机等)是不断向上盘旋。 SIP(系统在芯片)技术是一种强有力的手段实现小型化和制造这种高性能的电子设备。一些SIP协议的优势,在这样的电子设备提供全面的灵活性使用,由于其体积小,超薄型,以及高速的传输速率,低功耗,低成本,以获得最佳的全能技术相结合时。有几个可用的SIP方法;留学(系统封装)是最显着的,提供更快的时间将产品推向市场,它的易用性重新设计其最大的优势。特别是,被称为“螺旋式触头”(微接触技术)的PoP / SIP JISSO方法是通过先进系统日本(ASJ),它在3D提供的解决方案堆栈系统阵列创造了一个独特的市场。 3D堆叠技术体系的特点是:(1)只有KGD(已知合格芯片)将被累积,进而降低坏的产量问题最小的数字,当在半导体和电子零部件领域实施的限制是最小的。 (2)它也是允许制造商的能力和易于与规范工作特别是在存储器容量的变化等,因为它允许进行分层单独的芯片(或者在3D堆叠)非常灵活。 (3)将无源元件(电阻器,电容器,线圈等)的合并也是可能的。 (4)通过几个芯片组合成一个包缩短芯片间的布线距离。 (5)结果,EMI(电磁干扰)的影响噪声被降低,从而增加稳定性,同时提高高速运行。 (6)此外,对于微型计算机和存储器等之间的高速运转的布线的总线设计变得不必要,从而简化设计和减少在该过程的制造成本。 (7)其结果,上市时间大幅度减少。 (8),这使得它更容易,而不必担心昂贵的开发成本建立一个完整系统解决方案的建议。

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