Impact of Various JEDEC Drop Test Conditions on Board-level Reliability of Chip-scale Packages

摘要

In this study, reliability performances of board-level chip-scale packages subjected to four JEDEC drop test conditions: A (500 G; 1.0 ms), B (1500 G; 0.5 ms), F (900 G; 0.7 ms), and H (2900 G; 0.3 ms) were evaluated experimentally. Locations and modes of failed solder joints were examined using the dye stain test as well as a scanning electron microscope. To obtain thorough understanding of structural responses of the test vehicle and reliability of its solder joints under different test conditions, the transient finite element analysis was also performed.