A New Methodology to Design Low-Power Asynchronous Circuits

摘要

The aim of this paper is to present a new approach to creating high performance and low-power asynchronous circuits using high level design tools. In order to achieve this, we introduce a new timing model called Pseudo Delay-Insensitive model. To prove the goodness of this model, we present the results after comparing, for a set of benchmarks, our implementation with other implementations (synchronous and asynchronous).