System and method for performing automatic conversion from a synchronous circuit design representation to an asynchronous circuit design representation and from an asynchronous circuit design representation to a synchronous circuit design representation

摘要

Methods and systems for performing automated conversion of synchronous circuit design to asynchronous circuit design representations are described. A synchronous netlist may be generated from a synchronous circuit design. The synchronous netlist may include combinational logic gates and state-holding elements. The synchronous netlist may be converted to an asynchronous circuit design. The converting may include grouping the combinational logic gates by operations into functions.