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Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines

机译:CMOS门驱动传输线的操作区域建模与时序分析

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The switching behaviour and the operating region of a complementary metal-oxide-semiconductor (CMOS) gate driving a resistance-inductance-capacitance (RLC) transmission line is investigated in this paper. Closed form expressions for the time the transistors operate in the saturation and triode region respectively are proposed. Closed form expressions show predictions within 10% of HSPICE results for a wide range of line and buffer parameters, making them suitable to be applied to the problem of buffer sizing, repeater insertion, short circuit power estimation and generally whenevger the accurate knowledge of the operation of CMOS buffers driving a transmission line is required. In the paper useful hints for choosing the most appropriate model for the triode region of the transistors of the inductive-line driver are also given.
机译:本文研究了驱动电阻电容电容(RLC)传输线的互补金属氧化物半导体(CMOS)栅极的切换行为和操作区域。提出了晶体管在饱和度和三极管区域中操作的闭合形式表达式。封闭式表达式显示在Hspice的10%以上的预测,对于各种线和缓冲区参数,使其适用于缓冲器尺寸,中继器插入,短路功率估计的问题,并且一般是当efevger对操作的准确知识时需要驱动传输线的CMOS缓冲器。在本文中,还给出了用于选择电感线驱动器的晶体管的三极管区域的最合适模型的有用提示。

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