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A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors

机译:用于长指令字处理器的低能量聚类指令存储器层次结构

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In the current embedded processors for media applications, up to 30% of the total processor power is consumed in the instruction memory hierarchy. In this context, we present an inherently low energy clustered instruction memory hierarchy template. Small instruction memories are distributed over groups of functional units and the interconnects are localized in order to minimize energy consumption. Furthermore, we present a simple profile based algorithm to optimally synthesize the L0 clusters, for a given application. Using a few representative multimedia benchmarks we show that up to 45% of the L0 buffer energy can be reduced using our clustering approach.
机译:在目前媒体应用的嵌入式处理器中,在指令存储层次结构中消耗了高达30%的总处理器电源。在此上下文中,我们介绍了一个固有的低能量聚类指令记忆层次模板。小指令存储器分布在一组功能单元上,并且互连是本地化的,以便最小化能量消耗。此外,我们介绍了一种简单的基于型材的算法来最佳地合成给定应用程序的L0集群。使用少数代表多媒体基准测试,我们认为可以使用我们的聚类方法减少高达45%的L​​0缓冲能量。

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