Variable command decoding in a parallel digital signal processor for use with very large instruction words, whereby the words are broken down to variable length instruction parts for processing by separate processor units

摘要

Method for command decoding in a processor arrangement, especially a digital signal processor that comprises a number of synchronous data processing functional units, wherein an instruction word (VLIW) is formed from a number of instruction word parts (FIW). According to the method, within a predefined section of the instruction word, an instruction word part is captured and in response to the captured section, information for determination of a further section of the instruction word for decoding by a further decoding unit is determined. An independent claim is made for a processing arrangement, especially a digital signal processor.