With major price fluctuations of DRAM devices the semiconductor industry is investigating several processes to improve process yield and throughput to help reduce DRAM costs per die. One method the semiconductor industry is investigating to increase throughput is by using a high removal rate oxide process. In general, this requires a specific type of slurry. Presently the industry consensus is to use a ceria based slurry for high removal rate oxide processes. The throughput advantage here is to reduce present process times for planarizing ILD device structures from four to one minute. Theoretically this would increase the throughput by almost a factor of 4. In previous work we showed experimental data from a 112-wafer stability test using this slurry. In that work we measured an average removal rate of 5020-A/min and a WIWNU (1σ) of 4.78%. Furthermore, the initial and final removal rate of 4500-A/min and a 5200-A/min was measured, respectively. This corresponded to a Wafer-To-Wafer Removal Rate Variation (WTWRRV) of ～6%, and it was argued that this observed instability in the removal rate might be attributed to heat generated during the polishing process that caused irreversible damage to the insert material. It was further argued that in order to make high removal rate ceria slurry production worthy a new carrier head technology was needed to correct the observed instability in the removal rate and WIWNU. An alternative is to reduce the thermal load on the polishing pad. In this paper, we will compare a multi- and single-head CMP polishing. In particular a single head CMP polishing showed a reduction in the process instability by almost a factor of 5. In particular the WTWRRV was reduced from ～6% to 1.20%. In addition, we will further describe the experimental details carried out in this work that was carried out in order to make high removal rate ceria slurry production worthy.
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