It is known that significant intra-die thermal absorption variation is caused by non-optimized rapid thermal anneal (RTA) conditions and the variation depends on the local pattern density of various types of exposed stacks of the wafer. This variation can create errors in the electrical measurement MOSFET gate length itself. Two electrical methods for measuring gate length will be discussed, namely, the resistive technique, where a long-wide poly-silicon resistor is used as a normalizing resistor; and the capacitive technique, where a long-wide plate gate capacitor is used as a normalizing capacitor. It is shown, that the capacitive technique is more immune to errors introduced by RTA driven intra-die thermal absorption variation. Methods of minimizing these measurement errors are briefly discussed.
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