In this paper we state the relationship that output vectors of any true-faulty state pair must satisfy far the fault to be detectable at the primary outputs in one clack cycle. As an application, a new hardware scheme for easily testable PLA-based FSMs is proposed. With our scheme, all combinnationally irredundant faults in the PLA which result in unidirectional errors are testable. Moreover, test generation is easily accomplished because a) short systematic initialization sequences exist for each state in the machine, and b) a unit length distinguishing sequence, which holds under fault conditions, exits. In this paper we outline the scheme we propose, basically consisting in the addition of some state transitions and their outputs to the STG of the FSM. Experimental results on machines from the MCNC benchmark set for both the synthesis procedure and for the test generation process are given.
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