The stress profile around NMOS transistors is determined with CBED. The nitride spacers induce a mainly lateral compressive stress in the silicon substrate. The stress is three times higher for a 155 nm spacer than for a 100 nm spacer. The poly-silicon gate pulls at the silicon substrate inducing a tensile stress in the substrate, which is partially compensated by the compressive stress induced by the spacers. In the source/drain areas, ion implanted defects are observed. No stress is found in these regions.
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