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Strain at a semiconductor nanowire-substrate interface studied using geometric phase analysis, convergent beam electron diffraction and nanobeam diffraction

机译:使用几何相分析,会聚束电子衍射和纳米束衍射研究半导体纳米线 - 基底界面处的应变

摘要

Semiconductor nanowires have been studied using electron microscopy since the early days of nanowire growth, e.g. [1]. A common approach for analysing nanowires using transmission electron microscopy (TEM) involves removing them from their substrate and subsequently transferring them onto carbon films. This sample preparation method is fast and usually results in little structural change in the nanowires [2]. However, it does not provide information about the interface between the nanowires and the substrate, who’s physical and electrical properties are important for many modern applications of nanowires. In particular, strain and crystallographic defects can have a major influence on the electronic structure of the material. In improved method for the characterization of such interfaces would be valuable for optimizing and understanding the transport properties of devices based on nanowires. Here, we systematically investigate the interface between a nanowire and its substrate using three complementary methods for assessing strain. Results obtained using high resolution TEM for geometric phase analysis (GPA), convergent beam elecron diffraction (CBED) and nanobeam electron diffraction (NBED) are compared and contrasted. GPA measurements were acquired at 300kV in an FEI Titan 89-300 while the two diffraction methods were applied in the same microscope at 120kV. The GPA analysis software developed by C.T. Koch and V.B. Özdöl was used [3]. For samples other than nanowires, previous comparisons of GPA with CBED and NBED [4,5] have shown a high degree of consistency. Strain has previously only been measured in nanowires removed from their substrate [6], or only using GPA [7]. The sample used for the present investigation was an InP nanowire grown on a Si substrate using metal organic vapor phase deposition (MOCVD). Lattice missmatch between Si and InP is 8%. The nanowire had a diameter of approximately 100 nm in the interface area. TEM samples were prepared using a tripod polishing technique, with Ar ion milling used as the final thinning step. The resulting sample was clean and virtually free from defects from sample preparation. Measurements using all three techniques were obtained from the same well defined region of the specimen. Energy dispersive X-ray spectroscopy (EDS) maps were also acquired from the same area. Preliminary results acquired using GPA are shown in Figure 1. Whereas the base of the wire show some strain, little strain is observed in the substrate. The influence of defects, interfacial layers and compositional variations on the GPA will be discussed.
机译:自从纳米线生长的早期以来,例如,人们已经使用电子显微镜研究了半导体纳米线。 [1]。使用透射电子显微镜(TEM)分析纳米线的常用方法包括将纳米线从其基板上移除,然后将其转移到碳膜上。这种样品制备方法快速且通常导致纳米线的结构变化很小[2]。但是,它没有提供有关纳米线与基材之间界面的信息,而物理和电学性质对于纳米线的许多现代应用而言非常重要。特别是,应变和晶体学缺陷会对材料的电子结构产生重大影响。在用于表征这种界面的改进方法中,对于优化和理解基于纳米线的设备的传输特性将是有价值的。在这里,我们使用三种互补的评估应变的方法来系统地研究纳米线与其底物之间的界面。比较和对比了使用高分辨率TEM进行几何相分析(GPA),会聚束电子衍射(CBED)和纳米束电子衍射(NBED)所获得的结果。 GPA测量是在FEI Titan 89-300中以300kV进行的,而两种衍射方法是在同一显微镜下以120kV进行的。 C.T.开发的GPA分析软件科赫和V.B.使用了Özdöl[3]。对于纳米线以外的样品,以前的GPA与CBED和NBED的比较[4,5]已显示出高度的一致性。应变以前只能在从其基板上去除的纳米线中测量[6],或仅使用GPA [7]进行测量。用于本研究的样品是使用金属有机气相沉积(MOCVD)在Si衬底上生长的InP纳米线。 Si和InP之间的晶格失配为8%。纳米线在界面区域中具有约100nm的直径。使用三脚架抛光技术制备TEM样品,并将Ar离子铣削用作最终的稀释步骤。所得样品干净,几乎没有样品制备中的缺陷。从样品的同一明确区域获得使用这三种技术的测量值。能量色散X射线光谱(EDS)图也从同一区域获得。使用GPA获得的初步结果如图1所示。尽管线的底部显示出一定的应变,但在基板中观察到的应变很小。将讨论缺陷,界面层和成分变化对GPA的影响。

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