A 10-bit 200 MS/s parallel pipeline ADC is presented. It consists of a front-end sample-and-hold circuit and four parallel pipelined component ADCs followed by a digital offset compensation. By incorporating double sampling both in the S/H circuit and the component ADCs a power dissipation of only 280 mW from a 3.0 V supply is achieved. The circuit is implemented with a standard 0.5 μm CMOS process occupying 7.4 mm~2. According to the measurements, a DNL and INL of 0.8 LSB and 0.9 LSB, respectively, is achieved while the peak SFDR is 56 dB with a 200 MS/s sample rate.
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机译:提出了10位200 ms / s并行管道ADC。它包括前端采样和保持电路和四个并行流水线组件ADC,然后是数字偏移补偿。通过在S / H电路和分量ADC中加入双取样,实现了从3.0V电源的280 mW的功耗。电路采用标准0.5μmCMOS工艺实现,占据7.4mm〜2。根据测量,分别达到0.8LSB和0.9LSB的DNL和INL,同时峰值SFDR为56dB,采样率为200ms / s。
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